• JEDEC JEP147
Provide PDF Format

Learn More

JEDEC JEP147

  • PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)
  • standard by JEDEC Solid State Technology Association, 10/01/2003
  • Publisher: JEDEC

$27.00$53.00


This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics - to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component.

Related Products

JEDEC JESD 23

JEDEC JESD 23

TEST METHODS AND CHARACTER DESIGNATION FOR LIQUID CRYSTAL DEVICES:  ..

$37.00 $74.00

JEDEC JESD72 (R2007)

JEDEC JESD72 (R2007)

TEST METHODS AND ACCEPTANCE PROCEDURES FOR THE EVALUATION OF POLYMERIC MATERIALS..

$34.00 $67.00

JEDEC JEP155A.01

JEDEC JEP155A.01

RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION..

$46.00 $91.00

JEDEC JESD22-B110B

JEDEC JESD22-B110B

Mechanical Shock - Component and Subassembly..

$27.00 $54.00