Provide PDF Format
JEDEC JEP156
- CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
- standard by JEDEC Solid State Technology Association, 03/01/2009
- Publisher: JEDEC
$34.00$67.00
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.
Related Products
JEDEC JESD 82-26
DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS..
$37.00 $74.00
