• JEDEC JESD 24-2 (R2002)
Provide PDF Format

Learn More

JEDEC JESD 24-2 (R2002)

  • ADDENDUM No. 2 to JESD24 - GATE CHARGE TEST METHOD
  • Amendment by JEDEC Solid State Technology Association, 01/01/1991
  • Publisher: JEDEC

$27.00$53.00


This addendum establishes a method for measuring power device gate charge. A gate charge test is performed by driving the device gate with a constant current and measuring the resulting gate voltage response. Constant gate current scales the gate voltage, a function of time, to a function of coulombs. The slope of the generated response reflects the active device capacitance as it varies during the switching transition . Gate charge measurements are useful for characterizing the large signal switching performance of power MOS and IGBT devices. Developed over a four year span by the JEDEC JC-25 Committee, the method defines a repeatable means of measuring the widely published Qgd charge values.

Related Products

JEDEC JESD51-4

JEDEC JESD51-4

THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)..

$28.00 $56.00

JEDEC JESD230B

JEDEC JESD230B

NAND Flash Interface Interoperability..

$46.00 $91.00

JEDEC JESD531 (R2002)

JEDEC JESD531 (R2002)

THERMAL RESISTANCE TEST METHOD FOR SIGNAL AND REGULATOR DIODES (FORWARD VOLTAGE, SWITCHING METHOD)..

$30.00 $59.00

JEDEC JEP156

JEDEC JEP156

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION..

$34.00 $67.00