Provide PDF Format
JEDEC JESD 24-2 (R2002)
- ADDENDUM No. 2 to JESD24 - GATE CHARGE TEST METHOD
- Amendment by JEDEC Solid State Technology Association, 01/01/1991
- Publisher: JEDEC
$27.00$53.00
This addendum establishes a method for measuring power device gate charge. A gate charge test is performed by driving the device gate with a constant current and measuring the resulting gate voltage response. Constant gate current scales the gate voltage, a function of time, to a function of coulombs. The slope of the generated response reflects the active device capacitance as it varies during the switching transition . Gate charge measurements are useful for characterizing the large signal switching performance of power MOS and IGBT devices. Developed over a four year span by the JEDEC JC-25 Committee, the method defines a repeatable means of measuring the widely published Qgd charge values.
Related Products
JEDEC JESD 482-A (R2002)
LIST OF PREFERRED VALUES FOR USE ON VARIOUS TYPES OF SMALL SIGNAL AND REGULATOR DIODES..
$24.00 $48.00
JEDEC JESD 82-24
DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS..
$36.00 $72.00
