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JEDEC JESD 47G.01
- STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
- standard by JEDEC Solid State Technology Association, 04/01/2010
- Publisher: JEDEC
$34.00$67.00
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
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