Provide PDF Format
JEDEC JESD 78C
- IC LATCH-UP TEST
- standard by JEDEC Solid State Technology Association, 09/01/2010
- Publisher: JEDEC
$36.00$72.00
This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
Related Products
JEDEC JESD51-8
INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - JUNCTION-TO-BOARD..
$28.00 $56.00
JEDEC JESD 82-13A
DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100,..
$30.00 $59.00
JEDEC JEP150
STRESS-TEST-DRIVEN QUALIFICATION OF AND FAILURE MECHANISMS ASSOCIATED WITH ASSEMBLED SOLID STATE SUR..
$30.00 $60.00
JEDEC JESD73-4
STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH..
$26.00 $51.00