• JEDEC JESD203
Provide PDF Format

Learn More

JEDEC JESD203

  • STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES
  • standard by JEDEC Solid State Technology Association, 11/01/2005
  • Publisher: JEDEC

$26.00$51.00


This standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers. This standard is only intended to apply to devices released subsequent to the publication of this document.

Related Products

JEDEC JESD76-2

JEDEC JESD76-2

STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION)..

$24.00 $48.00

JEDEC JESD 24

JEDEC JESD 24

POWER MOSFETS..

$46.00 $91.00

JEDEC JESD22-B106D

JEDEC JESD22-B106D

RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICES..

$27.00 $53.00

JEDEC JESD82-17

JEDEC JESD82-17

DEFINITION OF THE SSTUA32S868 AND SSTUA32D868 REGISTERED BUFFER WITH PARITY FOR 2R X 4 DDR2 RDIMM AP..

$37.00 $74.00