• JEDEC JESD60A
Provide PDF Format

Learn More

JEDEC JESD60A

  • A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS
  • standard by JEDEC Solid State Technology Association, 09/01/2004
  • Publisher: JEDEC

$34.00$67.00


This method establishes a standard procedure for accelerated testing of the hot-carrier-induced change of a p-channel MOSFET. The objective is to provide a minimum set of measurements so that accurate comparisons can be made between different technologies. The measurements specified should be viewed as a starting pint in the characterization and benchmarking of the trasistor manufacturing process.

Related Products

JEDEC JP 002

JEDEC JP 002

CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINE..

$36.00 $72.00

JEDEC JESD47H

JEDEC JESD47H

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS..

$34.00 $67.00

JEDEC JESD8-16A

JEDEC JESD8-16A

BUS INTERCONNECT LOGIC (BIC) FOR 1.2 V..

$34.00 $67.00

JEDEC JESD22-A105C (R2011)

JEDEC JESD22-A105C (R2011)

POWER AND TEMPERATURE CYCLING..

$26.00 $51.00