Provide PDF Format
JEDEC JESD8-6
- ADDENDUM No. 6 to JESD8 - HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
- standard by JEDEC Solid State Technology Association, 08/01/1995
- Publisher: JEDEC
$30.00$60.00
This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz.
Related Products
JEDEC JESD3-C
STANDARD DATA TRANSFER FORMAT BETWEEN DATA PREPARATION SYSTEM AND PROGRAMMABLE LOGIC DEVICE PROGRAMM..
$39.00 $78.00
JEDEC JESD 12-4
ADDENDUM No. 4 to JESD12 - METHOD OF SPECIFICATION OF PERFORMANCE PARAMETERS FOR CMOS SEMICUSTOM INT..
$30.00 $60.00
JEDEC JESD22-A100-A
Solid State Devices, Testing Quality and Reliability - Test Method A100: Cycled Temperature Humidity..
$47.00 $93.00